I built a mod-16 counter, and the output result is a INTEGER (all the examples I saw used INTEGER). I built a hex-to-7-segment-display decoder, and its input is a STD_LOGIC_VECTOR (wrote it that way because it was easy to map out the truth table). I'd like to connect the output of the counter to the input of the decoder, but I get 'type mismatch' errors when trying to compile in QuartusII. Is there a way to convert from a INTEGER type to a STD_LOGIC_VECTOR type in a VHDL listing?
asked Sep 21, 2010 at 12:57 3,820 2 2 gold badges 28 28 silver badges 33 33 bronze badgesAs others said, use ieee.numeric_std , never ieee.std_logic_unsigned , which is not really an IEEE package.
However, if you are using tools with VHDL 2008 support, you can use the new package ieee.numeric_std_unsigned , which essentially makes std_logic_vector behave like unsigned.
Also, since I didn't see it stated explicitly, here's actual code example to convert from an (unsigned) integer to an std_logic_vector :
use ieee.numeric_std.all; . my_slv As LoneTech says, use ieee.numeric_std is your friend. You can convert a std_logic_vector to an integer , but you'll have to cast it as signed or unsigned first (as the compiler has no idea which you mean). VHDL is a strongly typed language. I've written more on this subject on my blog
Fundamentally, I'd change your 7seg converter to take in an integer (or actually a natural , given that it's only going to deal with positive numbers) - the conversion is then a simple array lookup. Set up a constant array with the conversions in and just index into it with the integer you use on the entity as an input.
answered Nov 17, 2010 at 14:51 Martin Thompson Martin Thompson 8,539 1 1 gold badge 25 25 silver badges 45 45 bronze badges\$\begingroup\$ Thanks for this. I appreciate your comments very much. I was in a TA position of sorts, learning VHDL to help a prof get started who was a little shakey on programming concepts. I'm going to pass on your info to him - the textbook we used didn't delve into VHDL 'morality' questions. \$\endgroup\$
Commented Nov 17, 2010 at 15:41\$\begingroup\$ It is less of a 'morality' issue than it is a guarantee of consistency. The numeric_std lib is a real standard instituted by the IEEE, while the std_logic_unsigned library was made up by a vendor, and adopted in the industry without any real formal definition. There is no guarantee of cross-vendor compatibility with the non-standard libs, though it typically works fine. It is good form to move on to the standard now though. \$\endgroup\$
Commented Sep 28, 2011 at 18:57 \$\begingroup\$To convert an integer to std_logic_vector you have several options. Using numeric_std:
vect vect vect std_logic_arith is a not an ieee standard, but most tools compile it into the IEEE library and it is widely used.
answered Oct 4, 2019 at 17:39 41 2 2 bronze badges \$\begingroup\$As the main answer says, the recommended method is as follows:
use ieee.numeric_std.all; . my_slv However, I would like to elaborate about why this is recommended, and why VHDL has such a seemingly convoluted way of converting integers into std_logic_vectors.
It comes down to how these types are viewed by the tools.
A standard_logic_vector is literally a bunch of 1s or 0s. I have 10001. What number is this? Well, it depends. Is it signed or unsigned? Ths SLV doesn't know or care. How many bits? Well, how long is your SLV?
An integer is signed, and usually 32 bits (if i remember correctly).
Stage 1: Make my integer shorter, and unsigned. That's this part:
to_unsigned(my_int, my_slv'length)); "I have this integer, I want it to be unsigned, and I want it to fit into the length of my SLV."
Stage 2: Then, take those bits and use them to drive the my_slv.
my_slv "Take these bits, and use them to drive my slv"
Combined, this gets you:
my_slv When coming from a traditional programming background, it's very easy to get stuck in a programming way of thinking. But in VHDL the code you write has physical implications in hardware. Knowing why this method works and is recommended is one step closer to thinking about what you're writing in hardware terms.
Bonus tip: functions prefixed by to_ are ones that shorten/change the operands. They make them unsigned or a certain length or both. This is why to_unsigned requires you to specify the length. The functions without to_ (straight std_logic_vector(. ) in this example) are used when types are directly compatible already. "Take these bits and stuff them in this type, no modifications required". These don't have a length argument because both sides are already the same. So when constructing things like this, I don't need to look it up, I just think about how I'm changing the data.